MODULE dcn2

TITLE 'dcn2'

"This version is UNFINISHED, but provides basic functioning for a 1581 clone
"20-May-2003
"Projects on the web at http://www.iki.fi/mkl
"The target CPLD is Lattice ispLSI1016-E80LJ, or other PLCC-44 ispLSI1016
"use Slowslew pin attribute when compiling design 
"This ABEL file describes three functionally separate modules. (In one file to save(?) trouble)
"1. Logic that replaces various IEC-bus related logic gates and buffers in the original CBM-1581
"2. Reset/Clock control logic that 
"(i) generates a delayed system reset to CPU, CIA and WD from master reset
"(ii) generates 2 MHz 6502 CPU clock PHI0, which MUST be running before reset is removed
"(iii) generates WD1772 clock, which is selectable between 8 or 16 MHz 
"3. Logic to control chip selects, output and write enables for RAM,(e)ROM,CIA,WD
"   and manage memory banks of 32 KByte RAM, and ROM (size 32, 64 or 128 KBytes)
"   and select the WD clock between 8 or 16 MHz
"   and select the floppy drive unit (Primary / Secondary)
"After master reset the signals are as follows:
"WD clock is 8 MHz (as in original 1581)
"Primary drive signal is active (low). The same signal will be high for secondary drive.
"Lowest 16 KB part of RAM is present at 6502 address $0000-$3fff
"CIA is visible at $4000-$4fff (registers at $4000-400f)
"WD is visible at $6000-$6fff (registers at $6000-6003)
"HIGHEST 32 Kbyte of ROM (PROM, ROM, EPROM or FLASH) is normally at $8000-$ffff
"SECOND LOWEST 4 KByte of ROM(ROM address $1000-1fff) is FIXED at $5000-$5fff. 
"A13 is copied to XA13 (the address pin on RAM/ROM)
"A14 is copied to XA14 (--""--)
"XA15 and XA16 are set to high
"XA13..XA16 outputs are for memory bank selection
"The configurable outputs and memory management get their input from CPU data line D7
"Address line A12 participates in selecting the configurable registers at $7000-$7fff
"The configuration data is fed SERIALLY from D7 using a special protocol algorithm.
"^^^^above function not yet implemented

"------------------------------------------------------------------------------------
"IEC logic part of design PIN DECLARATIONS
"IEC is a name for the Commodore serial bus
	DATA_IN pin 22; "inverted IEC_DATA line state from IEC BUS
		       "(signal from 74ls14 inverting schmitt trigger gate)
	DATA_OUT pin 19;  "output to 7406 inverting open collector driver to IEC_DATA line
	ATN_IN pin 20;    "IEC signal...
	FCLK_IN pin 21;   "IEC signal... 
	FCLK_OUT pin 18;  "IEC signal....
		"Note: IEC CLK line logic is not routed via this CPLD
"Signals from/to CIA
	DATAIN_CIA pin 4; "to CIA
	DATAOUT_CIA pin 5; "from CIA
	ATNIN_CIA pin 39; "to CIA
	ATNACK_CIA pin 6; "from CIA
	FASTDIR_CIA pin 7; "from CIA
	FASTCLK_CIA pin 10; "bi-directional from/to CIA
	FASTDATA_CIA pin 9; "bi-directional from/to CIA
"-------------------------------------------------------------------------------------
"-------------------------------------------------------------------------------------
"Control logic PART pin declarations
"inputs
	CLK pin 11;

	PHI2 pin 2;
	RnW pin 43;
	A12 pin 32;
	A13 pin 40;
	A14 pin 41;
	A15 pin 42;

	D7 pin 31;

"outputs
	PHI0 pin 44;
	nRESET pin 3 istype 'reg';
	WDCLK pin 16;

	nPRIMDRIVE pin 17;
	XA13 pin 26;
	XA14 pin 28;
	XA15 pin 38;
	XA16 pin 37;
	nWE pin 27;
	nOE pin 29;
	nCSROM pin 30;
	nCSRAM pin 25;
	nCSCIA pin 8;
	nCSWD pin 15;

"Internal stuff
	q7..q0 node istype 'reg';
	countteri = [q7..q0]; " set

"--------------------------------------------------------------------------------


"------- LOGIC EQUATIONS -------------------------------------------------------- 
equations
"IEC logic equations (this part is asynchronous logic)
	ATNIN_CIA = ATN_IN; "the signal is only passed to another pin on CPLD
	DATAIN_CIA = DATA_IN; "same here...
	DATA_OUT = DATAOUT_CIA # (ATN_IN & ATNACK_CIA) # (FASTDIR_CIA & !FASTDATA_CIA);
	"DATA_OUT is controlled by many sources...
	FCLK_OUT = FASTDIR_CIA & !FASTCLK_CIA;
	FASTDATA_CIA = (!DATA_IN);
	FASTCLK_CIA = (!FCLK_IN);
	FASTDATA_CIA.oe = !FASTDIR_CIA; "when FASTDIR is low, direction is towards the CIA
	FASTCLK_CIA.oe = !FASTDIR_CIA;  "and when high, towards the IEC BUS buffers.

"Control part equations
"All registers are reset to zero by the dedicated asynchronous reset input on the CPLD.
"Therefore, register asynchronous resets are not explicitly described.
"Clock & Reset output control
	countteri.clk = CLK; "clock is 32 MHz
	countteri:=countteri.fb+1; "counter function :-)
	PHI0=q3; "4 stages divide the frequency to 32->16->8->4->2 MHz
	nRESET.clk = q7; "asynchronous clocking...
	nRESET:='1'; " sets reset to inactive high	
	"WDCLK selection logic below....
	WDCLK=q1;
"simple....
	nPRIMDRIVE = '0';
	nWE = ! (!RnW & PHI2);
	nOE = ! RnW;
	when ([A15..A12]==5) then [XA16,XA15,XA14,XA13] = [0,0,0,0];
			else      [XA16,XA15,XA14,XA13] = [1,1,A14,A13]; "ROM banking
	"chip selects
	nCSROM =! ((A15==1) # ([A15..A12]==5));" $8000-ffff + $5000-$5fff
	nCSRAM =! ([A15,A14]==[0,0]); "$0000-$3fff
	nCSCIA =! ([A15..A12]==4); "$4000-$4fff
	nCSWD  =! (([A15..A12]==6) & PHI2); "$6000-$6fff, phi2 is involved...
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     

END